6.0 The Constraints File
Vivado has a lot of different ways to do the same thing. The case of mapping signals to pins on the FPGA is no exception. For instance, we can use the Constraints Wizard or we can look at the FPGA package view and map signals that way. Both of these methods are just ways of doing the same thing, though: modifying a constraints file.
In this example, the package pins and various other properties have already been set. Take a look at clocked_led.xdc. You'll see a handful of PACKAGE_PIN lines that do exactly this:
set_property PACKAGE_PIN E19 [get_ports clk_pin_p]
set_property PACKAGE_PIN E18 [get_ports clk_pin_n]
set_property PACKAGE_PIN AM39 [get_ports {led_pins[0]}]
set_property PACKAGE_PIN AN39 [get_ports {led_pins[1]}]
set_property PACKAGE_PIN AR37 [get_ports {led_pins[2]}]
set_property PACKAGE_PIN AT37 [get_ports {led_pins[3]}]
set_property PACKAGE_PIN AR35 [get_ports {led_pins[4]}]
set_property PACKAGE_PIN AP41 [get_ports {led_pins[5]}]
set_property PACKAGE_PIN AP42 [get_ports {led_pins[6]}]
set_property PACKAGE_PIN AU39 [get_ports {led_pins[7]}]
set_property PACKAGE_PIN AV40 [get_ports rst_pin]
Take another look at the VC707 schematic and you'll see that all of the pin assignments made above make sense. E19 and E18 are the pins that are connected to the input clock and AM39, AN39, AR37, AT37, AR35, AP41, AP42, and AU39 are connected to the output LEDs. AV40 is the CPU_RESET button on the board.
There are also lines to set the IOSTANDARDS, DRIVE strengths, and SLEW rates of the OBUF signals as well.
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[3]}]
set_property DRIVE 12 [get_ports {led_pins[0]}]
set_property DRIVE 12 [get_ports {led_pins[1]}]
set_property DRIVE 12 [get_ports {led_pins[2]}]
set_property DRIVE 12 [get_ports {led_pins[3]}]
set_property SLEW SLOW [get_ports {led_pins[0]}]
set_property SLEW SLOW [get_ports {led_pins[1]}]
set_property SLEW SLOW [get_ports {led_pins[2]}]
set_property SLEW SLOW [get_ports {led_pins[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[4]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[5]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[6]}]
set_property IOSTANDARD LVCMOS15 [get_ports {led_pins[7]}]
set_property DRIVE 12 [get_ports {led_pins[4]}]
set_property DRIVE 12 [get_ports {led_pins[5]}]
set_property DRIVE 12 [get_ports {led_pins[6]}]
set_property DRIVE 12 [get_ports {led_pins[7]}]
set_property SLEW SLOW [get_ports {led_pins[4]}]
set_property SLEW SLOW [get_ports {led_pins[5]}]
set_property SLEW SLOW [get_ports {led_pins[6]}]
set_property SLEW SLOW [get_ports {led_pins[7]}]
Vivado also requires that we set the CONFIG_VOLTAGE and the CFGBVS voltage at some point. This is a bit beyond the scope of this tutorial, but for more information check here.
At this point, we're ready to start buiding our design.
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Table Of Contents
- Part 1: Getting Started
- Part 2: Creating the Project in Vivado
- Part 3: Taking a Look at the VHDL Source Code
- Part 4: Creating clk_core With the Clocking Wizard
- Part 5: Source Code for the LED Controller
- Part 6: The Constraints File clocked_led.xdc
- Part 7: Elaborating, Synthesizing, and Implementing
- Part 8: Generating and Downloading the Bitstream